用STATECAD快速设计有限状态机(2)

宏模块使用Pterms Used寄存器使用情况引脚使用情况IOB使用情况
9/36 (25%)37/180 (21%)9/36 (25%)13/34 (39%)11/72 (16%)

进行引脚锁定后就可以进行编程。
代码如下：
-- D:\XILINXTUTORIAL\VCRSTATE.vhd
-- VHDL code created by Xilinx's StateCAD 6.1i

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY VCRSTATE IS
PORT (CLK,PLAYSWITCH,POWERSWITCH,RECORDSWITCH,RESET,STOPSWITCH: IN std_logic;
PLAYLED,POWERLED,RECORDLED : OUT std_logic);
END;

ARCHITECTURE BEHAVIOR OF VCRSTATE IS
TYPE type_sreg IS (OFF,PLAY,POWERON,RECORDING);
SIGNAL sreg, next_sreg : type_sreg;
SIGNAL next_PLAYLED,next_POWERLED,next_RECORDLED : std_logic;
BEGIN
PROCESS (CLK, RESET, next_sreg, next_PLAYLED, next_POWERLED, next_RECORDLED)
BEGIN
IF ( RESET='1' ) THEN
sreg