module mx7541(clk,a,b,in,out);
output out;
input a,b,clk;
input[7..0]in;
reg[7..0]out;
reg[7..0] di;
reg[7..0]gao;
always @(negedge clk)
begin
if(a==0 & b==1)
di<=in;
else
if(a==1 & b